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Preliminary Technical Data
FEATURES
8-channel DAC in 52-LQFP and 56-LFCSP Guaranteed monotonic to 16/14 bits Nominal output voltage range of -10 V to +10 V Multiple output spans available Temperature Monitoring Function Channel Monitoring Multiplexer GPIO Function System calibration function allowing user-programmable offset and gain Channel grouping and addressing features Data error checking feature
8-Channel, 16/14-Bit, Serial Input, Voltage-Output DAC AD5362/AD5363
SPI compatible serial interface 2.5 V to 5.5 V JEDEC-compliant digital levels Power-on reset Digital reset (RESET) Clear function to user-defined SIGGND (CLR pin) Simultaneous update of DAC outputs (LDAC pin)
APPLICATIONS
Instrumentation Industrial Control System PLC Analog I/O Cards Level setting in automatic test equipment (ATE) Variable optical attenuators (VOA) Precision Medical Instruments
FUNCTIONAL BLOCK DIAGRAM
DVCC VDD VSS AGND DNGD LDAC
TEMP_OUT PEC MON_IN0 MON_IN1
TEMP SENSOR CONTROL REGISTER VOUT0 VOUT7 6 MUX 8
AD5362, n = 16 AD5363, n = 14 4 n n n A/B SELECT 4 REGISTER n X1 REGISTER n M REGISTER C REGISTER TO MUX 2's n A/B MUX X2A REGISTER X2B REGISTER
VREF0 14 14 OFS0 REGISTER n DAC 0 OFFSET DAC 0 BUFFER MUX n 2 DAC 0 REGISTER OUTPUT BUFFER AND POWER DOWN CONTROL BUFFER GROUP 0
VOUT0
n
MON_OUT 2 GPIO BIN/2SCOMP SYNC SDI SCLK SDO BUSY SERIAL INTERFACE GPIO REGISTER
* * * * * *
n n n
n n
* * * * * *
n
* * * * * *
n
* * * * * *
A/B MUX
* * * * * *
X1 REGISTER M REGISTER C REGISTER
X2A REGISTER X2B REGISTER
MUX n 2
* * * * * *
n DAC 3 REGISTER
* * * * * *
* * * * * *
DAC 3
* * * * * *
OUTPUT BUFFER AND POWER DOWN CONTROL
VOUT1
VOUT2
VOUT3
SIGGND0
GROUP 1 14 OFS1 REGISTER 14 OFFSET DAC 1 BUFFER X2A REGISTER X2B REGISTER MUX n 2 n DAC 0 REGISTER DAC 0 OUTPUT BUFFER AND POWER DOWN CONTROL
VREF1
4 RESET CLR STATE MACHINE n n n n
A/B SELECT 4 REGISTER n X1 REGISTER n M REGISTER C REGISTER
TO MUX 2's n A/B MUX n
VOUT4
* * * * * *
POWER-ON RESET
n n
n n
* * * * * *
n
* * * * * *
n
* * * * * *
A/B MUX
* * * * * *
* * * * * *
MUX 2
X1 REGISTER M REGISTER C REGISTER
X2A REGISTER X2B REGISTER
n
n DAC 3 REGISTER
* * * * * *
* * * * * *
DAC 3
* * * * * *
OUTPUT BUFFER AND POWER DOWN CONTROL
VOUT5
VOUT6
VOUT7 SIGGND1
AD5362/ AD5363
n
5362-0001B
Figure 1.
AD5362/AD5363--Protected by U.S. Patent No. 5,969,657; other patents pending
Rev. PrF
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.
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AD5362/AD5363 TABLE OF CONTENTS
General Description ......................................................................... 3 Specifications..................................................................................... 4 AC Characteristics........................................................................ 5 Timing Characteristics ................................................................ 6 Absolute Maximum Ratings............................................................ 8 ESD Caution.................................................................................. 8 Pin Configuration and Function Descriptions............................. 9 Terminology .................................................................................... 11 Functional Description .................................................................. 12 DAC Architecture--General..................................................... 12 Channel Groups.......................................................................... 12 A/ B Registers And Gain/Offset Adjustment.......................... 13 Offset DACs ................................................................................ 13 Output Amplifier........................................................................ 14 Transfer Function ....................................................................... 14 Reference Selection .................................................................... 14 Calibration................................................................................... 15 AD5362 Calibration Example................................................... 15 Reset Function ............................................................................ 15 Clear Function ............................................................................ 16
Preliminary Technical Data
BUSY and LDAC Functions...................................................... 16 BIN/2s Comp Pin ....................................................................... 16 Temperature Sensor ................................................................... 16 Monitor Function....................................................................... 16 GPIO Pin ..................................................................................... 17 Power-Down Mode.................................................................... 17 Temperature Monitoring........................................................... 17 Toggle Mode................................................................................ 17 Serial Interface ................................................................................ 18 SPI Write Mode .......................................................................... 18 Register Update Rates ................................................................ 18 SPI Readback Mode ................................................................... 19 Channel Addressing And Special Modes................................ 19 Special Function Mode.............................................................. 20 Power Supply Decoupling ......................................................... 22 Power Supply Sequencing ......................................................... 22 Interfacing Examples ................................................................. 23 Outline Dimensions ....................................................................... 24 Ordering Guide .......................................................................... 24
REVISION HISTORY
Rev Pr B1 Rev Pr B2
Rev Pr F
Added Reference Selection and Calibration Text Modified SPI Timing Diagrams
Rewrote calibration section Changed SPI read diagram
Rev. PrF | Page 2 of 25
Preliminary Technical Data GENERAL DESCRIPTION
The AD5362/AD5363 contains 8, 16/14-bit DACs in a single, 56-lead, LFCSP or 52-lead LQFP package. It provides buffered voltage outputs with a span 4 times the reference voltage. The gain and offset of each DAC can be independently trimmed to remove errors. For even greater flexibility, the device is divided into two groups of 4 DACs, and the output range of each group can be independently adjusted by an offset DAC. The AD5362/AD5363 offers guaranteed operation over a wide supply range with VSS from -4.5 V to -16.5 V and VDD from +8 V to +16.5 V. The output amplifier headroom requirement is 1.4 V operating with a load current of 1 mA.
AD5362/AD5363
The AD5362/AD5363 has a high-speed serial interface, which is compatible with SPI(R), QSPITM, MICROWIRETM, and DSP interface standards and can handle clock speeds of up to 50 MHz. All the outputs can be updated simultaneously by taking the LDAC input low. Each channel has a programmable gain and an offset adjust register. Each DAC output is amplified and buffered on-chip with respect to an external SIGGND input. The DAC outputs can also be switched to SIGGND via the CLR pin
Table 1. High Channel Count Bipolar DACs
Model AD5360BCPZ AD5360BSTZ AD5361BCPZ AD5361BSTZ AD5362BCPZ AD5362BSTZ AD5363BCPZ AD5363BSTZ AD5370BCPZ AD5370BSTZ AD5371BCPZ AD5371BSTZ AD5372BCPZ AD5372BSTZ AD5373BCPZ AD5373BSTZ Resoluti on 16 Bits 16 Bits 14 Bits 14 Bits 16 Bits 16 Bits 14 Bits 14 Bits 16 Bits 16 Bits 14 Bits 14 Bits 16 Bits 16 Bits 14 Bits 14 Bits Nominal Output Span 4 x VREF (20 V) 4 x VREF (20 V) 4 x VREF (20 V) 4 x VREF (20 V) 4 x VREF (20 V) 4 x VREF (20 V) 4 x VREF (20 V) 4 x VREF (20 V) 4 x VREF (12 V) 4 x VREF (12 V) 4 x VREF (12 V) 4 x VREF (12 V) 4 x VREF (12 V) 4 x VREF (12 V) 4 x VREF (12 V) 4 x VREF (12 V) Output Channels 16 16 16 16 8 8 8 8 40 40 40 40 32 32 32 32 Linearity Error (LSB) 4 4 1 1 4 4 1 1 4 4 2 2 4 4 2 2 Package Description 56-Lead LFCSP 52-Lead LQFP 56-Lead LFCSP 52-Lead LQFP 56-Lead LFCSP 52-Lead LQFP 56-Lead LFCSP 52-Lead LQFP 64-Lead LFCSP 64-Lead LQFP 100-Ball CSPBGA 80-Lead LQFP 56-Lead LFCSP 64-Lead LQFP 56-Lead LFCSP 64-Lead LQFP Package Option CP-56 ST-52 CP-56 ST-52 CP-56 ST-52 CP-56 ST-52 CP-64 ST-64 BC-100-2 ST-80 CP-56 ST-64 CP-56 ST-64
Rev. PrF | Page 3 of 25
AD5362/AD5363 SPECIFICATIONS
Preliminary Technical Data
DVCC = 2.3 V to 5.5 V; VDD = 8 V to 16.5 V; VSS = -4.5 V to -16.5 V; VREF = 3 V; AGND = DGND = SIGGND = 0 V; RL = Open Circuit; Gain (m), Offset(c) and DAC Offset registers at default value; all specifications TMIN to TMAX, unless otherwise noted. Table 2. Performance Specifications
Parameter ACCURACY Resolution Relative Accuracy Differential Nonlinearity Offset Error Gain Error Offset Error2 Gain Error2 Gain Error of Offset DAC VOUT Temperature Coefficient DC Crosstalk2 REFERENCE INPUTS (VREF0, VREF1)2 VREF DC Input Impedance VREF Input Current VREF Range SIGGND INPUT (SIGGND0 TO SIGGND4)2 DC Input Impedance Input Range OUTPUT CHARACTERISTICS2 Output Voltage Range Short Circuit Current Load Current Capacitive Load DC Output Impedance MONITOR PIN (MON_OUT) Output Impedance Three State Leakage Current Continuous Current Limit DIGITAL INPUTS Input High Voltage Input Low Voltage Input Current (with pull-up/pulldown) Input Current (no pull-up/pull-down) Input Capacitance2 DIGITAL OUTPUTS (SDO) Output Low Voltage Output High Voltage (SDO) High Impedance Leakage Current High Impedance Output Capacitance2 B Version 1 16 14 4 1 -1/+1.5 20 20 100 100 35 5 0.5 Unit Bits Bits LSB max LSB max LSB max mV max mV max V max V max mV max ppm FSR/C typ mV max Test Conditions/Comments2 AD5362 AD5363 AD5362 AD5363 Guaranteed monotonic by design over temperature. Prior to calibration Prior to calibration After to calibration After to calibration Positive or Negative Full Scale. See Offset DACs section for details Includes linearity, offset, and gain drift. Typically 100 V. Measured channel at mid-scale, full-scale change on any other channel Typically 100 M. Per input. Typically 30 nA. 2% for specified operation. Typically 60 k.
1 60 2/5 55 0.5 VSS + 2 VDD - 2 5 1 2200 1 500 100 2 1.7 2.0 0.8 8 1 10 0.5 DVCC - 0.5 -5 10
M min nA max V min/max k min V min/max V min V max mA max mA max pF max max typ nA typ mA max V min V min V max A max A max pF max V max V min A max pF typ
ILOAD = 1 mA. ILOAD = 1 mA.
JEDEC compliant. IOVCC = 2.5 V to 3.6 V. IOVCC = 3.6 V to 5.5 V. IOVCC = 2.5 V to 5.5 V. CLR and RESET pin only. All other digital input pins.
Sinking 200 A. Sourcing 200 A. SDO only.
Rev. PrF | Page 4 of 25
Preliminary Technical Data
Parameter POWER REQUIREMENTS DVCC VDD VSS Power Supply Sensitivity2 Full Scale/ VDD Full Scale/ VSS Full Scale/ VCC DICC IDD ISS Power Dissipation Power Dissipation Unloaded (P) Junction Temperature3 B Version 1 2.3/5.5 8/16.5 -4.5/-16.5 -75 -75 -90 2 5 5 350 130 Unit V min/max V min/max V min/max dB typ dB typ dB typ mA max mA max mA max mW C max Test Conditions/Comments2
AD5362/AD5363
VCC = 5.5 V, VIH = VCC, VIL = GND. Outputs unloaded. Outputs unloaded.
TJ = TA + PTOTAL x J.
1 2
Temperature range for B Version: -40C to +85C. Typical specifications are at 25C. Guaranteed by design and characterization, not production tested. 3 Where J represents the package thermal impedance.
AC CHARACTERISTICS
DVCC = 2.5 V; VDD = 15 V; VSS = -15 V; VREF = 3 V; AGND = DGND = SIGGND = 0 V; CL = 200pF; RL = 10 k; Gain (m), Offset(c) and DAC Offset registers at default value; all specifications TMIN to TMAX, unless otherwise noted. Table 3. AC Characteristics
Parameter DYNAMIC PERFORMANCE1 Output Voltage Settling Time Slew Rate Digital-to-Analog Glitch Energy Glitch Impulse Peak Amplitude Channel-to-Channel Isolation DAC-to-DAC Crosstalk Digital Crosstalk Digital Feedthrough Output Noise Spectral Density @ 10 kHz
1
B Version 20 30 1 20 10 100 40 10 0.1 1 250
Unit s typ s max V/s typ nV-s typ mV max dB typ nV-s typ nV-s typ nV-s typ nV-s typ nV/(Hz)1/2 typ
Test Conditions/Comments Full-scale change DAC latch contents alternately loaded with all 0s and all 1s.
VREF = 2 V p-p, 1 kHz. Between DACs in the same group. Between DACs from different groups. Effect of input bus activity on DAC output under test. VREF = 0 V.
Guaranteed by design and characterization. Not production tested
Rev. PrF | Page 5 of 25
AD5362/AD5363
TIMING CHARACTERISTICS
Preliminary Technical Data
DVCC = 2.3 V to 5.5 V; VDD = 8 V to 16.5 V; VSS = -4.5 V to -16.5 V; VREF = 3 V; AGND = DGND = SIGGND = 0 V; RL = Open Circuit; Gain (m), Offset(c) and DAC Offset registers at default value; all specifications TMIN to TMAX, unless otherwise noted. SPI INTERFACE (Figure 4 and Figure 5)
Parameter1, 2, 3 t1 t2 t3 t4 t5 t6 t7 t8 t93 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t225
1 2 3
Limit at TMIN, TMAX 20 8 8 11 20 10 5 4.5 42 1.25 500 20 10 3 0 3 20/30 125 30 400 270 25
Unit ns min ns min ns min ns min ns min ns min ns min ns min ns max
Description SCLK Cycle Time. SCLK High Time. SCLK Low Time. SYNC Falling Edge to SCLK Falling Edge Setup Time. Minimum SYNC High Time. 24th SCLK Falling Edge to SYNC Rising Edge. Data Setup Time. Data Hold Time. SYNC Rising Edge to BUSY Falling Edge. BUSY Pulse Width Low (Single-Channel Update.) See Table 7 Single-Channel Update Cycle Time 24th SCLK Falling Edge to LDAC Falling Edge. LDAC Pulse Width Low. BUSY Rising Edge to DAC Output Response Time. BUSY Rising Edge to LDAC Falling Edge. LDAC Falling Edge to DAC Output Response Time. DAC Output Settling Time. CLR/RESET Pulse Activation Time. RESET Pulse Width Low. RESET Time Indicated by BUSY Low. Minimum SYNC High Time in Readback Mode. SCLK Rising Edge to SDO Valid.
s max
ns max ns min ns min
s max
ns min
s max
s typ/max ns max ns min s max ns min ns max
Guaranteed by design and characterization, not production tested. All input signals are specified with tr = tf = 2 ns (10% to 90% of VCC) and timed from a voltage level of 1.2 V. See Figure 4 and Figure 5. 4 This is measured with the load circuit of Figure 2 5 This is measured with the load circuit of Figure 3.
V CC
200A IOL
RL TO OUTPUT PIN
2.2k
TO OUTPUT PIN
CL
50pF 200A IOL
V OH (min) - V OL (max) 2
V OL CL 50pF
Figure 2. Load Circuit for BUSY Timing
Figure 3. Load Circuit for SDO Timing Diagram
Rev. PrF | Page 6 of 25
Preliminary Technical Data
t1
SCLK
1 2 24 1 24
AD5362/AD5363
t3 t4
SYNC
t2 t6
t11
t5 t7 t8
SDI
DB23
DB0
t9
BUSY
t10
t12
LDAC1
t13 t17 t14 t15 t13
VOUT1
LDAC2
t17
VOUT2
t 16
CLR
t18
VOUT
t19
RESET
VOUT
t18 t20
05814-004A
BUSY
1LDAC ACTIVE DURING BUSY. 2LDAC ACTIVE AFTER BUSY.
Figure 4. SPI Write Timing
t22 SCLK
24 t21
48
SYNC
SDI
DB23
DB0
DB23
DB0
INPUT WORD SPECIFIES REGISTER TO BE READ SDO
5371-0005D
NOP CONDITION
DB0
DB23
DB0
LSB FROM PREVIOUS WRITE
SELECTED REGISTER DATA CLOCKED OUT
Figure 5. SPI Read Timing
Rev. PrF | Page 7 of 25
AD5362/AD5363 ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted. Transient currents of up to 100 mA do not cause SCR latch-up. Table 4. Absolute Maximum Ratings
Parameter VDD to AGND VSS to AGND DVCC to DGND Digital Inputs to DGND Digital Outputs to DGND VREF0, VREF1 to AGND VOUT0-VOUT7 to AGND SIGGND to AGND AGND to DGND Operating Temperature Range (TA) Industrial (B Version) Storage Temperature Range Junction Temperature (TJ max) Reflow Soldering Peak Temperature Time at Peak Temperature Rating -0.3 V to +17 V -17 V to +0.3 V -0.3 V to +7 V -0.3 V to VCC + 0.3 V -0.3 V to VCC + 0.3 V -0.3 V to +5.5 V VSS - 0.3 V to VDD + 0.3 V 1 V -0.3 V to +0.3 V -40C to +85C -65C to +150C 150C 230C 10 s to 40 s
Preliminary Technical Data
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. PrF | Page 8 of 25
Preliminary Technical Data PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
CLR LDAC AGND DGND DVCC SDO PEC SDI SCLK SYNC DVCC DGND NC NC
AD5362/AD5363
DGND
DGND
AGND
DVCC
SYNC
DVCC
SCLK
SDO
PEC
SDI
NC
NC
56 55 54 53 52 51 50 49 48 47 46 45 44 43
52 51 50 49 48 47 46 45 44 43 42 41 40
LDAC
RESET BIN/2SCOMP BUSY GPIO MON_OUT MON_IN0 NC NC NC NC NC VDD VSS VREF1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 42 41 40 39 38 37 36 35 34 33 32 31 30 29 NC NC SIGGND0 VOUT3 VOUT2 VOUT1 VOUT0 TEMP_OUT MON_IN1 VREF0 NC NC VSS VDD
NC
1 2 3 4 5 6 7 8 9 10 11 12 13 5362-060414
39
NC SIGGND0 VOUT3 VOUT2 VOUT1 VOUT0 TEMP_OUT MON_IN1 VREF0 NC VSS VDD NC
PIN 1 INDICATOR
CLR RESET BIN/2SCOMP BUSY GPIO MON_OUT MON_IN0 NC NC VDD VSS VREF1
PIN 1 INDICATOR
38 37 36
AD5362/ AD5363 TOP VIEW (Not to scale)
AD5362/ AD5363 TOP VIEW (Not to scale)
35 34 33 32 31 30 29 28 27
NC = NO CONNECT
NC 15 NC 16 VOUT4 17 VOUT5 18 VOUT6 19 VOUT7 20 SIGGND1 21 NC 22 NC 23 NC 24 NC 25 NC 26 NC 27 NC 28
5362LFCSP060414
NC = NO CONNECT
NC VOUT4 VOUT5 NC NC NC VOUT6 NC VOUT7 NC NC SIGGND1 NC
Figure 6. 56 Lead LFCSP Pin Configuration
Figure 7. 52 Lead LQFP Pin Configuration
Table 5. Pin Function Descriptions
Pin Name DVCC VSS VDD AGND DGND SIGGND0 SIGGND1 VREF0 VREF1 VOUT0 to VOUT15 SYNC SCLK SDI SDO LDAC BUSY RESET CLR PEC TEMP_OUT MON_OUT MON_IN0, MON_IN1 Function Logic Power Supply; 2.3 V to 5.5 V. These pins should be decoupled with 0.1 F ceramic capacitors and 10 F capacitors. Negative Analog Power Supply; -11.4 V to -16.5 V for specified performance. These pins should be decoupled with 0.1 F ceramic capacitors and 10 F capacitors. Positive Analog Power Supply; +11.4 V to +16.5 V for specified performance. These pins should be decoupled with 0.1 F ceramic capacitors and 10 F capacitors. Ground for All Analog Circuitry. All AGND pins should be connected to the AGND plane. Ground for All Digital Circuitry. All DGND pins should be connected to the DGND plane. Reference Ground for DACs 0 to 3. VOUT0 to VOUT3 are referenced to this voltage. Reference Ground for DACs 4 to 7. VOUT4 to VOUT7 are referenced to this voltage. Reference Input for DACs 0 to 3. This voltage is referred to AGND. Reference Input for DACs 4 to 7. This voltage is referred to AGND. DAC Outputs. Buffered analog outputs for each of the 16 DAC channels. Each analog output is capable of driving an output load of 10 k to ground. Typical output impedance of these amplifiers is 0.5 . Active Low or SYNC Input for SPI Interface. This is the frame synchronization signal for the SPI serial interface. See SPI timing diagrams and descriptions for more details. Serial Clock Input for SPI Interface. See SPI timing diagrams and descriptions for more details. Serial Data Input for SPI Interface. See SPI timing diagrams and descriptions for more details. Serial Data Output for SPI Interface. See SPI timing diagrams and descriptions for more details. Load DAC Logic Input (Active Low). See the BUSY and LDAC FUNCTIONS section for more information. Digital Input/Open-Drain Output. BUSY is open-drain when an output. See the BUSY and LDAC FUNCTIONS section for more information Asynchronous Digital Reset Input Asynchronous clear input (level sensitive, active low). See the Clear Function section for more information Packet Error Check output. This is an open-drain output with a 50 k pullup, that goes low if the packet error check fails. Provides an output voltage proportional to chip temperature. This is typically 1.5 V at 25 C with an output variation of 5 mV/C. Analog multiplexer output. Any DAC output or the MON_IN0 or the MON_IN1 input can be switched to this output. Analog multiplexer inputs, which can be switched to MON_OUT.
Rev. PrF | Page 9 of 25
AD5362/AD5363
Pin Name GPIO BIN/2SCOMP EXPOSED PADDLE
Preliminary Technical Data
Function Digital I/O pin. This pin can be configured as an input or output that can be read or programmed high or low via the serial interface. When configured as an input it has a weak pulldown. Digital input, sets the DAC coding. 0 = offset binary, 1 = 2's complement. This input has a weak pulldown. The Lead Free Chip Scale Package (LFCSP) has an exposed paddle on the underside. This should be connected to VSS
Rev. PrF | Page 10 of 25
Preliminary Technical Data TERMINOLOGY
Relative Accuracy Relative accuracy, or endpoint linearity, is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for zero-scale error and full-scale error and is expressed in least significant bits (LSB). Differential Nonlinearity Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of 1 LSB maximum ensures monotonicity. Zero-Scale Error Zero-scale error is the error in the DAC output voltage when all 0s are loaded into the DAC register. Zero-scale error is a measure of the difference between VOUT (actual) and VOUT (ideal) expressed in mV. Zero-scale error is mainly due to offsets in the output amplifier. Full-Scale Error Full-scale error is the error in DAC output voltage when all 1s are loaded into the DAC register. Full-scale error is a measure of the difference between VOUT (actual) and VOUT (ideal) expressed in mV. It does not include zero-scale error. Gain Error Gain error is the difference between full-scale error and zero-scale error. It is expressed in mV. Gain Error = Full-Scale Error - Zero-Scale Error VOUT Temperature Coefficient This includes output error contributions from linearity, offset, and gain drift. DC Output Impedance DC output impedance is the effective output source resistance. It is dominated by package lead resistance.
AD5362/AD5363
DC Crosstalk The DAC outputs are buffered by op amps that share common VDD and VSS Vpower supplies. If the dc load current changes in one channel (due to an update), this can result in a further dc change in one or more channel outputs. This effect is more significant at high load currents and reduces as the load currents are reduced. With high impedance loads, the effect is virtually immeasurable. Multiple VDD and VSS terminals are provided to minimize dc crosstalk. Output Voltage Settling Time The amount of time it takes for the output of a DAC to settle to a specified level for a full-scale input change. Digital-to-Analog Glitch Energy The amount of energy injected into the analog output at the major code transition. It is specified as the area of the glitch in nV-s. It is measured by toggling the DAC register data between 0x1FFF and 0x2000. Channel-to-Channel Isolation Channel-to-channel isolation refers to the proportion of input signal from one DAC's reference input that appears at the output of another DAC operating from another reference. It is expressed in dB and measured at midscale. DAC-to-DAC Crosstalk DAC-to-DAC crosstalk is the glitch impulse that appears at the output of one converter due to both the digital change and subsequent analog output change at another converter. It is specified in nV-s. Digital Crosstalk The glitch impulse transferred to the output of one converter due to a change in the DAC register code of another converter is defined as the digital crosstalk and is specified in nV-s. Digital Feedthrough When the device is not selected, high frequency logic activity on the device's digital inputs can be capacitively coupled both across and through the device to show up as noise on the VOUT pins. It can also be coupled along the supply and ground lines. This noise is digital feedthrough. Output Noise Spectral Density Output noise spectral density is a measure of internally generated random noise. Random noise is characterized as a spectral density (voltage per Hz). It is measured by loading all DACs to midscale and measuring noise at the output. It is measured in nV/(Hz)
1/2
Rev. PrF | Page 11 of 25
AD5362/AD5363 FUNCTIONAL DESCRIPTION
DAC ARCHITECTURE--GENERAL
The AD5362/AD5363 contains 8 DAC channels and 8 output amplifiers in a single package. The architecture of a single DAC channel consists of a 16-bit resistor-string DAC in the case of the AD5362 and a 14-bit DAC in the case of the AD5363, followed by an output buffer amplifier. The resistor-string section is simply a string of resistors, each of value R, from VREF to AGND. This type of architecture guarantees DAC monotonicity. The 16(14)-bit binary digital code loaded to the DAC register determines at which node on the string the voltage is tapped off before being fed into the output amplifier. The output amplifier multiplies
Preliminary Technical Data
the DAC out voltage by 4. The output span is 12 V with a 3 V reference and 20 V with a 5 V reference.
CHANNEL GROUPS
The 16 DAC channels of the AD5362/AD5363 are arranged into two groups of 8 channels. The eight DACs of Group 0 derive their reference voltage from VREF0, and those of Group 1 from VREF1
Table 6. AD5362(AD5363) Registers
Register Name X1A (group)(channel) X1B (group) (channel) M (group) (channel) C (group) (channel) X2A (group)(channel) Word Length (Bits) 16(14) 16(14) 16(14) 16(14) 16(14) Description Input data register A, one for each DAC channel. Input data register B, one for each DAC channel. Gain trim registers, one for each DAC channel. Offset trim registers, one for each DAC channel. Output data register A, one for each DAC channel. These registers store the final, calibrated DAC data after gain and offset trimming. They are not readable, nor directly writable. Output data register B, one for each DAC channel. These registers store the final, calibrated DAC data after gain and offset trimming. They are not readable, nor directly writable. Data registers from which the DACs take their final input data. The DAC registers are updated from the X2A or X2B registers. They are not readable, nor directly writable. 14 14 8 Offset DAC 0 data register, sets offset for Group 0. Offset DAC 1 data register, sets offset for Group 1. Bit 4 = Overtemperature indicator. 1 = chip temperature > 130 C. Bit 3 = PEC error flag. 1 = PEC error. Cleared on reading control register. Bit 2 = A/B. 0 = global selection of X1A input data registers. 1 = X1B registers. Bit 1 = Enable Temp Shutdown. 0 = disable temp shutdown. 1 = enable. Bit 0 = Soft Power Down. 0 = soft power up. 1 = soft power down. Monitor 6 Bit 5 = Monitor enable. 0 = off. 1 = on. Bit 4 = 0, DAC selected by bits 3 to 0. Bits 3 - 0 = DAC channel 0000 = 0 to 1111 = 15. Bit 4 = 1, MON_IN pin selected by bit 0. Bit 0 = MON_IN select. 0 = MON_IN0. 1 = MON_IN1. GPIO 2 Bit 1 = GPIO configuration. 0 = input. 1 = output. Bit 0 = GPIO data. Stores state of GPIO pin when input. Drives GPIO pin when output.
X2B (group) (channel)
16(14)
DAC (group) (channel) OFS0 OFS1 Control
Rev. PrF | Page 12 of 25
Preliminary Technical Data
A/ B REGISTERS AND GAIN/OFFSET ADJUSTMENT
Each DAC channel has seven data registers. The actual DAC data word can be written to either the X1A or X1B input register, depending on the setting of the A/B bit in the Control Register. If the A/B bit is 0, data will be written to the X1A register. If the A/B bit is 1, data will be written to the X1B register. Note that this single bit is a global control and affects every DAC channel in the device. It is not possible to set up the device on a per-channel basis so that some writes are to X1A registers and some writes are to X1B registers.
X1A REGISTER MUX X1B REGISTER M REGISTER C REGISTER X2B REGISTER X2A REGISTER MUX
AD5362/AD5363
All DACs in the AD5362/AD5363 can be updated simultaneously by taking LDAC low, when each DAC register will be updated from either its X2A or X2B register, depending on the setting of the A/B select registers. The DAC register is not readable, nor directly writable by the user.
OFFSET DACS
In addition to the gain and offset trim for each DAC, there are two 14-bit Offset DACs, one for Group 0, and one for Group 1. These allow the output range of all DACs connected to them to be offset within a defined range. Thus, subject to the limitations of headroom, it is possible to set the output range of Group 0, and/or Group 1 to be unipolar positive, unipolar negative, or bipolar, either symmetrical or asymmetrical about zero volts. The DACs in the AD5362/AD5363 are factory trimmed with the Offset DACs set at their default values. This gives the best offset and gain performance for the default output range and span. When the output range is adjusted by changing the value of the Offset DAC an extra offset is introduced due to the gain error of the Offset DAC. The amount of offset is dependent on the magnitude of the reference and how much the Offset DAC moves from its default value. This offset is quoted on the specification page. The worst case offset occurs when the Offset DAC is at positive or negative full-scale. This value can be added to the offset present in the main DAC of a channel to give an indication of the overall offset for that channel. In most cases the offset can be removed by programming the channels C register with an appropriate value. The extra offset cause by the Offset DACs only needs to be taken into account when the Offset DAC is changed from its default value. Figure 9 shows the allowable code range which may be loaded to the Offset DAC and this is dependant on the reference value used. Thus, for a 5V reference, the Offset DAC should not be programmed with a value greater than 8192 (0x2000).
5 RESERVED
DAC REGISTER
DAC
Figure 8. Data Registers Associated With Each DAC Channel
Each DAC channel also has a gain (M) and offset (C) register, which allow trimming out of the gain and offset errors of the entire signal chain. Data from the X1A register is operated on by a digital multiplier and adder controlled by the contents of the M and C registers. The calibrated DAC data is then stored in the X2A register. Similarly, data from the X1B register is operated on by the multiplier and adder and stored in the X2B register. Although a multiplier and adder symbol are shown for each channel, there is only one multiplier and one adder in the device, which are shared between all channels. This has implications for the update speed when several channels are updated at once, as described later. Each time data is written to the X1A register, or to the M or C register with the A/B control bit set to 0, the X2A data is recalculated and the X2A register is automatically updated. Similarly, X2B is updated each time data is written to X1B, or to M or C with A/B set to 1. The X2A and X2B registers are not readable, nor directly writable by the user. Data output from the X2A and X2B registers is routed to the final DAC register by a multiplexer. Whether each individual DAC takes its data from the X2A or X2B register is controlled by an 8-bit A/B Select Register associated with each group of 8 DACs. If a bit in this register is 0, the DAC takes its data from the X2A register; if 1 the DAC takes its data from the X2B register (bit 0 controls DAC 0 through bit 7 controls DAC 7). Note that, since there are 8 bits in 2 registers, it is possible to set up, on a per-channel basis, whether each DAC takes its data from the X2A or X2B register. A global command is also provided that sets all bits in the A/B Select Registers to 0 or to 1.
4
VREF (V)
3
2
0 0
4096
8192 12288 OFFSET DAC CODE
16383
Figure 9. Offset DAC Code Range
Rev. PrF | Page 13 of 25
5370-0200
1
AD5362/AD5363
OUTPUT AMPLIFIER
As the output amplifiers can swing to 1.4 V below the positive supply and 1.4 V above the negative supply, this limits how much the output can be offset for a given reference voltage. For example, it is not possible to have a unipolar output range of 20V, since the maximum supply voltage is 16.5 V.
DAC CHANNEL S2 CLR R5 R1 R3 R2 SIGGND CHECK VALUE OF R1 &R5 R1,R2,R3 = 20k R4,R5 = 60k R6 = 10k CLR CLR S3 R4 SIGGND OFFSET DAC
2049-0008
Preliminary Technical Data
OFFSET_CODE is the 14-bit code written to the offset DAC register. As this DAC is a 14 bit device, the code is multiplied by 4 to make the transfer function correct, since the X, M and C registers are 16-bit. The default value for the Offset DAC is 8192 (0x2000) AD5363 Code applied to DAC from X1A or X1B register:DAC_CODE = INPUT_CODE x (m+1)/214 + c - 213 DAC output voltage:VOUT = 4 x VREF x (DAC_CODE - OFFSET_CODE )/214 +VSIGGND Notes DAC_CODE should be within the range of 0 to 16383. For 12 V span VREF = 3.0 V. For 20 V span VREF = 5.0 V. X1A, X1B default code = 8192 m = code in gain register; default m code = 214 - 1. c = code in offset register; default c code = 213. OFFSET_CODE is the code loaded to the offset DAC. The default value for the Offset DAC is 8192 (0x2000)
S1
OUTPUT R6 10k
Figure 10. Output Amplifier and Offset DAC
Figure 10 shows details of a DAC output amplifier and its connections to the Offset DAC. On power up, S1 is open, disconnecting the amplifier from the output. S3 is closed, so the output is pulled to SIGGND. S2 is also closed to prevent the output amplifier being open-loop. If CLR is low at power-up, the output will remain in this condition until CLR is taken high. The DAC registers can be programmed, and the outputs will assume the programmed values when CLR is taken high. Even if CLR is high at power-up, the output will remain in the above condition until VDD > 6 V and VSS < -4 V and the initialization sequence has finished. The outputs will then go to their poweron default value.
REFERENCE SELECTION
The AD5362/AD5363 has two reference input pins. The voltage applied to the reference pins determines the output voltage span on VOUT0 to VOUT7. VREF0 determines the voltage span for VOUT0 to VOUT3 and VREF1 determines the voltage span for VOUT4to VOUT7. The reference voltage applied to each VREF pin can be different, if required, allowing each group of 4 channels to have a different voltage span. The output voltage range can be adjusted further by programming the offset and gain registers for each channel as well as programming the offset DAC. If the offset and gain features are not used (i.e. the m and c registers are left at their default values) the required reference levels can be calculated as follows: VREF = (VOUTmax - VOUTmin)/4 If the offset and gain features of the AD5362AD5363are used, then the required output range is slightly different. The chosen output range should take into account the system offset and gain errors that need to be trimmed out. Therefore, the chosen output range should be larger than the actual, required range. The required reference levels can be calculated as follows: 1. 2. 3. Identify the nominal output range on VOUT. Identify the maximum offset span and the maximum gain required on the full output signal range. Calculate the new maximum output range on VOUT including the expected maximum offset and gain errors. Choose the new required VOUTmax and VOUTmin, keeping the VOUT limits centered on the nominal
TRANSFER FUNCTION
From the foregoing, it can be seen that the output voltage of a DAC in the AD5362/AD5363 depends on the value in the input register, the value of the M and C registers, and the offset from the Offset DAC. The transfer function is given by: AD5362 Code applied to DAC from X1A or X1B register:DAC_CODE = INPUT_CODE x (m+1)/216 + c - 215 DAC output voltage:VOUT = 4 x VREF x (DAC_CODE - OFFSET_CODE x 4 )/216 +VSIGGND Notes DAC_CODE should be within the range of 0 to 65535 For 12 V span VREF = 3.0 V. For 20 V span VREF = 5.0 V. X1A, X1B default code = 32768 m = code in gain register; default m code = 216 - 1. c = code in offset register; default c code = 215.
4.
Rev. PrF | Page 14 of 25
Preliminary Technical Data
values. Note that VDD and VSS must provide sufficient headroom. 5. Calculate the value of VREF as follows: VREF = (VOUTMAX - VOUTMIN)/4
AD5362/AD5363
the C register. Note that only negative zero-scale error can be reduced. Full-scale error can be reduced as follows: 1. 2. 3. Measure the zero-scale error. Set the output to the highest possible value. Measure the actual output voltage and compare it with the required value. Add this error to the zero-scale error. This is the full-scale error. Calculate the number of LSBs equivalent to the full-scale error and subtract it from the default value of the M register. Note that only positive full-scale error can be reduced. The M and C registers should not be programmed until both zero-scale and full-scale errors have been calculated.
Reference Selection Example
Nominal Output Range = 20V (-10V to +10V) Offset Error = 100mV Gain Error = 3% SIGGND = AGND = 0V 1) Gain Error = 3% => Maximum Positive Gain Error = +3% => Output Range incl. Gain Error = 20 + 0.03(20)=20.6V Offset Error = 100mV => Maximum Offset Error Span = 2(100mV)=0.2V => Output Range including Gain Error and Offset Error = 20.6V + 0.2V = 20.8V VREF Calculation Actual Output Range = 20.6V, that is -10.3V to +10.3V (centered); VREF = (10.3V + 10.3V)/4 = 5.15V
4.
2)
5.
3)
AD5362 CALIBRATION EXAMPLE
This example assumes that a -10 V to +10 V output is required. The DAC output is set to -10 V but measured at -10.03 V. This gives an zero-scale error of -30 mV. 1. 1 LSB = 20 V/65536 = 305.176 V 30 mV = 98 LSB 98 LSB should be added to the default C register value: (32768 + 98) = 32866 32866 should be programmed to the C register
If the solution yields an inconvenient reference level, the user can adopt one of the following approaches: 1. 2. Use a resistor divider to divide down a convenient, higher reference level to the required level. Select a convenient reference level above VREF and modify the Gain and Offset registers to digitally downsize the reference. In this way the user can use almost any convenient reference level but may reduce the performance by overcompaction of the transfer function. Use a combination of these two approaches
2. 3. 4.
The full-scale error can now be removed. The output is set to +10 V and a value of +10.02 V is measured. The full-scale error is +20 mV - (-30 mV) = +50 mV This is a full-scale error of +50 mV. 1. 50 mV = 164 LSBs 164 LSB should be subtracted from the default M register value: (65535 - 164) = 65371 65371 should be programmed to the M register
3.
CALIBRATION
The user can perform a system calibration on the AD5362 and AD5363 to reduce gain and offset errors to below 1 LSB. This is achieved by calculating new values for the M and C registers and reprogramming them.
2. 3.
RESET FUNCTION
When the RESET pin is taken low, the DAC buffers are disconnected and the DAC outputs VOUT0 to VOUT7 are tied to their associated SIGGND signals via a 10 k resistor. On the rising edge of RESET the AD5362/AD5363 state machine initiates a reset sequence to reset the X, M and C registers to their default values. This sequence typically takes 300s and the user should not write to the part during this time. When the reset sequence is complete, and provided that CLR is high, the DAC output will be at a potential specified by the default
Reducing Zero-scale and Full-scale Error
Zero-scale error can be reduced as follows: 1. 2. 3. Set the output to the lowest possible value. Measure the actual output voltage and compare it with the required value. This gives the zero-scale error. Calculate the number of LSBs equivalent to the error and subtract this from the default value of
Rev. PrF | Page 15 of 25
AD5362/AD5363
register settings which will be equivalent to SIGGGND. The DAC outputs will remain at SIGGND until the X, M or C registers are updated and LDAC is taken low.
Action
Preliminary Technical Data
Table 7. BUSY Pulse Widths
BUSY Pulse Width (s max) 1.25 1.75 4.75
CLEAR FUNCTION
CLR is an active low input which should be high for normal operation. The CLR pin has in internal 500k pull-down resistor. When CLR is low, the input to each of the DAC output buffer stages, VOUT0 to VOUT7, is switched to the externally set potential on the relevant SIGGND pin. While CLR is low, all LDAC pulses are ignored. When CLR is taken high again, the DAC outputs remain cleared until LDAC is taken low. The contents of input registers and DAC registers 0 to 7 are not affected by taking CLR low. To prevent glitches appearing on the outputs CLR should be brought low whenever the output span is adjusted by writing to the offset DAC.
Loading X1A, X1B, C, or M to 1 channel Loading X1A, X1B, C, or M to 2 channels Loading X1A, X1B, C, or M to 8 channels
BUSY Pulse Width = ((Number of Channels +1) x 500ns) +250ns
The AD5362/AD5363 contains an extra feature whereby a DAC register is not updated unless its X2A or X2B register has been written to since the last time LDAC was brought low. Normally, when LDAC is brought low, the DAC registers are filled with the contents of the X2A or X2B registers, depending on the setting of the A/B Select Registers. However the AD5362/AD5363 updates the DAC register only if the X2 data has changed, thereby removing unnecessary digital crosstalk.
BUSY AND LDAC FUNCTIONS
The value of an X2 (A or B) register is calculated each time the user writes new data to the corresponding X1, C, or M registers. During the calculation of X2, the BUSY output goes low. While BUSY is low, the user can new data to the X1, M, or C registers, provided the first stage of the calculation is complete (see the Register Update Rates section for more details). The BUSY pin is bidirectional and has a 50 k internal pullup resistor. Where multiple AD5362 or AD5363 devices may be used in one system the BUSY pins can be tied together. This is useful where it is required that no DAC in any device is updated until all other DACs are ready. When each device has finished updating the X2 (A or B) registers it will release the BUSY pin. If another device hasn't finished updating its X2 registers it will hold BUSY low, thus delaying the effect of LDAC going low. The DAC outputs are updated by taking the LDAC input low. If LDAC goes low while BUSY is active, the LDAC event is stored and the DAC outputs update immediately after BUSY goes high. A user can also hold the LDAC input permanently low. In this case, the DAC outputs update immediately after BUSY goes high. BUSY also goes low, for approximately 500ns, whenever the A/B Select Registers are written to. As described later, the AD5362/AD5363 has flexible addressing that allows writing of data to a single channel, all channels in a group, or all channels in the device. This means that several register values may need to be calculated and updated. As there is only one multiplier shared between 8 channels, this task must be done sequentially, so the length of the BUSY pulse will vary according to the number of channels being updated.
BIN/2S COMP PIN
The BIN/2SCOMP pin determines if the input data is interpreted as offset binary or 2's complement. If this pin is low, then the data is binary. If it is 1, the data is interpreted as 2's complement. This affects only the X, C, and Offset DAC registers. The M register data and all control and command data is interpreted as straight binary.
TEMPERATURE SENSOR
The on-chip temperature sensor provides a voltage output at the TEMP_OUT pin that is linearly proportional to the Centigrade temperature scale. The typical accuracy of the temperature sensor is 1C at +25C and 5C over the -40C to +85C range. Its nominal output voltage is 1.5V at +25C, varying at 5 mV/C, giving a typical output range of 1.175V to 1.9 V over the full temperature range. Its low output impedance, low self heating, and linear output simplify interfacing to temperature control circuitry and A/D converters.
MONITOR FUNCTION
The AD5362/AD5363 contains a channel monitor function that consists of an analog multiplexer addressed via the serial interface, allowing any channel output to be routed to this pin for monitoring using an external ADC. In addition, two monitor inputs, MON_IN0 and MON_IN1 are provided, which can also be routed to MON_OUT. The monitor function is controlled by the Monitor Register, which allows the monitor output to be enabled or disabled, and selection of a DAC channel or one of the monitor pins. When disabled, the monitor output is high impedance, so several monitor outputs may be connected in parallel and only one enabled at a time. Table 8 shows the control register settings relevant to the monitor function.
Rev. PrF | Page 16 of 25
Preliminary Technical Data
Table 8. Control Register Monitor Functions
F5 0 1 1 1 1 1 1 F4 X X 0 0 0 1 1 F3 X X 0 0 0 0 0 F2 X X 0 0 1 0 0 F1 X X 0 0 1 0 0 F0 X X X 1 1 0 1 MON_OUT Disabled MON_OUT Enabled MON_OUT = VOUT0 MON_OUT = VOUT1 MON_OUT = VOUT7 MON_OUT = MON_IN0 MON_OUT = MON_IN1
AD5362/AD5363
TOGGLE MODE
The AD5362/AD5363 has two X2 registers per channel, X2A and X2B, which can be used to switch the DAC output between two levels with ease. This approach greatly reduces the overhead required by a micro-processor which would otherwise have to write to each channel individually. When the user writes to either the X1A ,X2A, M or C registers the calculation engine will take a certain amount of time to calculate the appropriate X2A or X2B values. If the application only requires that the DAC output switch between two levels, such as a data generator, any method which reduces the amount of calculation time encountered is advantageous. For the data generator example the user need only set the high and low levels for each channel once, by writing to the X1A and X1B registers. The values of X2A and X2B will be calculated and stored in their respective registers. The calculation delay therefore only happens during the setup phase, i.e. when programming the initial values. To toggle a DAC output between the two levels it is only required to write to the relevant A/B Select Register to set the MUX2 register bit. Furthermore, since there are 4 MUX2 control bits per register it is possible to update four channels with a single write. Table 12 shows the bits that correspond to each DAC output.
The multiplexer is implemented as a series of analog switches. Since this could conceivably cause a large amount of current to flow from the input of the multiplexer, i.e. VOUTx or MON_INx to the output of the multiplexer, MON_OUT, care should taken to ensure that whatever is connected to the MON_OUT pin is of high enough impedance to prevent the Continuous Current Limit specification from being exceeded.
GPIO PIN
The AD5362/AD5363 has a general-purpose I/O pin, GPIO. This can be configured as an input or an output and read back or programmed (when configured as an output) via the serial interface. Typical applications for this pin include monitoring the status of a logic signal, limit switch, or controlling an external multiplexer. The GPIO pin is configured by writing to the GPIO register, which has the special function code of 0b001101 (see Table 11 and Table 13 ). When Bit F1 is set the GPIO pin will be an output and F0 will determine whether the pin is high or low. The GPIO pin can be set as an input by writing 0 to both F1 and F0. The status of the GPIO pin can be determined by initiating a read operation using the appropriate bits in Table 14. The status of the pin will be indicated by the LSB of the register read.
POWER-DOWN MODE
The AD5362/AD5363 can be powered down by setting Bit 0 in the control register. This will turn off the DACs thus reducing the current consumption. The DAC outputs will be connected to their respective SIGGND potentials. The power-down mode doesn't change the contents of the registers and the DACs will return to their previous voltage when the power-down bit is cleared.
TEMPERATURE MONITORING
The AD5362/AD5363 can be programmed to power down the DACs if the temperature on the die exceeds 130C. Setting Bit 1 in the control register (see Table 13) will enable this function. If the die temperature exceeds 130C the AD5362/AD5363 will enter a temperature power-down mode, which is equivalent to setting the power-down bit in the control register. To indicate that the AD5362/AD5363 has entered temperature shutdown mode Bit 4 of the control register is set. The AD5362/AD5363 will remain in temperature shutdown mode, even if the die temperature falls, until Bit 1 in the control register is cleared.
Rev. PrF | Page 17 of 25
AD5362/AD5363 SERIAL INTERFACE
The AD5362/AD5363 contains an SPI-compatible interface operating at clock frequencies up to 50MHz (20MHz for read operations). To minimize both the power consumption of the device and on-chip digital noise, the interface powers up fully only when the device is being written to, that is, on the falling edge of SYNC. The serial interface is 2.5 V LVTTL compatible when operating from a 2.3 V to 3.6 V DVCC supply. It is controlled by four pins, as follows.
Preliminary Technical Data
500ns each and the third stage takes 250ns. When the write to one of the X1, C or M registers is complete the calculation process begins. If the write operation involves the update of a single DAC channel the user is free to write to another register provided that the write operation doesn't finish until the first stage calculation is complete, i.e. 500ns after the completion of the first write operation. If a group of channels is being updated by a single write operation the first stage calculation will be repeated for each channel, taking 500ns per channel. In this case the user should not complete the next write operation until this time has elapsed.
SYNC
Frame synchronization input.
PACKET ERROR CHECKING
To verify that data has been received correctly in noisy environments, the AD5362/AD5363 offers the option of error checking based on an 8-bit (CRC-8) cyclic redundancy check. The device controlling the AD5362/AD5363 should generate an 8-bit frame check sequence using the polynomial C(x) = x8 + x2 + x1 +1. This is added to the end of the data word, and 32 data bits are sent to the AD5362/AD5363 before taking SYNC high. If the AD5362/AD5363 sees a 32-bit data frame, it will perform the error check when SYNC goes high. If the check is valid, then the data will be written to the selected register. If the error check fails, the Packet Error Check output (PEC) will go low and bit 3 of the Control Register is set. After reading this register, this error flag is cleared automatically and PEC goes high again.
UPDATE ON SYNC HIGH SYNC
SDI
Serial data input pin.
SCLK
Clocks data in and out of the device.
SPI WRITE MODE
The AD5362/AD5363 allows writing of data via the serial interface to every register directly accessible to the serial interface, which is all registers except the X2A and X2B registers and the DAC registers. The X2A and X2B registers are updated when writing to the X1A, X1B, M and C registers, and the DAC registers are updated by LDAC. The serial word (see Tables 7 and 8) is 24 bits long. 16(14) of these bits are data bits, five bits are address bits, and two bits are mode bits that determine what is done with the data. The serial interface works with both a continuous and a burst (gated) serial clock. Serial data applied to SDI is clocked into the AD5362/AD5363 by clock pulses applied to SCLK. The first falling edge of SYNC starts the write cycle. At least 24 falling clock edges must be applied to SCLK to clock in 24 bits of data, before SYNC is taken high again. If SYNC is taken high before the 24th falling clock edge, the write operation will be aborted. If a continuous clock is used, and PEC mode isn't used, SYNC must be taken high before the 25th falling clock edge. This inhibits the clock within the AD5362/AD5363. If more than 24 falling clock edges are applied before SYNC is taken high again, the input data will be corrupted. If an externally gated clock of exactly 24 pulses is used, SYNC may be taken high any time after the 24th falling clock edge. The input register addressed is updated on the rising edge of SYNC. In order for another serial transfer to take place, SYNC must be taken low again.
SCLK MSB D23 DIN 24-BIT DATA LSB D0
24-BIT DATA TRANSFER - NO ERROR CHECKING UPDATE AFTER SYNC HIGH ONLY IF ERROR CHECK PASSED
SYNC
SCLK MSB D31 DIN 24 BIT DATA LSB D8 D7 D0 8-BIT FCS
PEC
PEC GOES LOW IF ERROR CHECK FAILS 24-BIT DATA TRANSFER WITH ERROR CHECKING
5360-0010
REGISTER UPDATE RATES
As mentioned previously the value of the X2 (A or B) register is calculated each time the user writes new data to the corresponding X1, C or M registers. The calculation is performed by a three stage process. The first two stages take
Rev. PrF | Page 18 of 25
Figure 10. SPI Write With and Without Error Checking
Preliminary Technical Data
Table 7. AD5362 Serial Word Bit Assignation
I23 M1 I22 M0 I21 A5 I20 A4 I19 A3 I18 A2 I17 A1 I16 A0 I15 D15 I14 D14 I13 D13 I12 D12 I11 D11 I10 D10 I9 D9 I8 D8 I7 D7 I6 D6 I5 D5 I4 D4
AD5362/AD5363
I3 D3
I2 D2
I1 D1
I0 D0
Table 8. AD5363 Serial Word Bit Assignation
I23 M1 I22 M0 I21 A5 I20 A4 I19 A3 I18 A2 I17 A1 I16 A0 I15 D13 I14 D12 I13 D11 I12 D10 I11 D9 I10 D8 I9 D7 I8 D6 I7 D5 I6 D4 I5 D3 I4 D2 I3 D1 I2 D0 I1* 0 I0* 0
M1 and M0 are mode bits. A5 is an unused address bit and must always be written as 0. A4 to A0 are address bits. D15 to D0 are data bits. *In the AD5363, bits I1 and I0 are only used in Special Function Mode
SPI READBACK MODE
The AD5362/AD5363 allows data readback via the serial interface from every register directly accessible to the serial interface, which is all registers except the X2A, X2B and DAC registers. In order to read back a register, it is first necessary to tell the AD5362/AD5363 which register is to be read. This is achieved by writing to the device a word whose first two bits are the special function code 00. The remaining bits then determine if the operation is a readback, and the register which is to be read back, or if it is a write to of the special function registers such as the control register. After the special function write has been performed, if it is a readback command then data from the selected register will be clocked out of the SDO pin during the next SPI operation. The SDO pin is normally three-state but becomes driven as soon as a read command has been issued. The pin will remain driven until the registers data has been clocked out. See Figure 5 for the read timing diagram. Note that due to the timing requirements of t5 (25ns) the maximum speed of the SPI interface during a read operation should not exceed 20MHz.
CHANNEL ADDRESSING AND SPECIAL MODES
If the mode bits are not 00, then the data word D15 to D0 is written to the device. Address bits A4 to A0 determine which channel or channels is/are written to, while the mode bits determine to which register (X1A, X1B, C or M) the data is written, as shown in Table 7. If data is to be written to the X1A or X1B register, the setting of the A/B bit in the Control Register determines which (0 X1A, 1 X1B). Table 9. Mode Bits M1
1 1 0 0
M0
1 0 1 0
Action
Write DAC input data (X1A or X1B) register, depending on Control Register A/B bit. Write DAC offset (C) register Write DAC gain (M) register Special function, used in combination with other bits of word
The AD5362/AD5363 has very flexible addressing that allows writing of data to a single channel, all channels in a group, the same channel in groups 0 and 1, or all channels in the device. Table 11 shows all these address modes.
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AD5362/AD5363
Preliminary Technical Data
Table 10.Group and Channel Addressing This table shows which group(s) and which channel(s) is/are addressed for every combination of address bits A4 to A0.
ADDRESS BITS A4 TO A3
00 000 001 010 All groups, all channels Group 0, all channels Group 1, all channels Unused Unused Unused Unused Unused 01 Group 0, channel 0 Group 0, channel 1 Group 0, channel 2 Group 0, channel 3 Unused Unused Unused Unused 10 Group 1, channel 0 Group 1, channel 1 Group 1, channel 2 Group 1, channel 3 Unused Unused Unused Unused 11 Unused Unused Unused Unused Unused Unused Unused Unused
ADDRESS BITS A2 TO A0
011 100 101 110 111
SPECIAL FUNCTION MODE
If the mode bits are 00, then the special function mode is selected, as shown in Table 12. Bits I21 to I16 of the serial data word select the special function, while the remaining bits are Table 11. Special Function Mode
I23 0 I22 0 I21 S5 I20 S4 I19 S3 I18 S2 I17 S1 I16 S0 I15 F15 I14 F14 I13 F13 I12 F12 I11 F11
data required for execution of the special function, for example the channel address for data readback. The codes for the special functions are shown in Table 13. Table 14 shows the addresses for data readback.
I10 F10 I9 F9 I8 F8 I7 F7 I6 F6 I5 F5 I4 F4 I3 F3 I2 F2 I1 F1 I0 F0
Table 12. DACs Select by A/B Select Registers
A/B Select Register 0 1 Bits F7 Not Used Not Used F6 Not Used Not Used F5 Not Used Not Used F4 Not Used Not Used F3 VOUT3 VOUT7 F2 VOUT2 VOUT6 F1 VOUT1 VOUT5 F0 VOUT0 VOUT4
Rev. PrF | Page 20 of 25
Preliminary Technical Data
Table 13. Special Function Codes
SPECIAL FUNCTION CODE S5 0 0 S4 0 0 S3 0 0 S2 0 0 S1 0 0 S0 0 1 DATA F15-F0 0000 0000 0000 0000 XXXX XXXX XXX[F4:F0] NOP ACTION
AD5362/AD5363
Write control register F4 = 1 Over-temperature; F4 = 0 Temp OK (Read-only bit) F3 = 1 PEC error; F3 = 0 PEC OK (Read-only bit) F2 = 1 F2 = 0 F1 = 1 F1 = 0 F0 = 1 Select B Register for input; Select A Register for input Enable temperature shutdown; Disable temperature shutdown Soft power down; F0 = 0 Soft power up
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 1
0 0 1 1 1 1
1 1 0 1 1 0
0 1 1 0 1 0
[F13:F0] [F13:F0] See Table 14 XXXX XXXX XXXX [F3:F0] XXXX XXXX XXXX [F3:F0] XXXX XXXX XX[F5:F0]
Write data in F13:F0 to OFS0 register Write data in F13:F0 to OFS1 register Select register for readback Write data in F3:F0 to A/B Select Register 0 (Group 0) Write data in F3:F0 to A/B Select Register 1 (Group 1) F5 = 1 Monitor enable; F5 = 0 Monitor disable F4 = 1 Monitor input pin selected by F0 (0 = MON_IN0, 1 = MON_IN1) F4 = 0 Monitor DAC channel selected by F3:F0 (0000 = channel 0 0111 = channel 7) GPIO configure and write F1 = 1 GPIO is output. Data to output is written to F0 F1 = 0 GPIO is input. Data can be read from F0 on readback
0
0
1
1
0
1
XXXX XXXX XXXX XX[F1:F0]
Note. When writing to the offset registers, the 14-bit data is right justified (bits F15 and F14 are don't care). When writing to the X, M or C registers of the AD5363, the 14-bit data is left-justified (bits 1 and 0 of the data word are don't care).
Table 14. Address Codes for Data Readback
F15 0 0 0 0 1 1 1 1 1 1
1 2
F14 0 0 1 1 0 0 0 0 0 0
F13 0 1 0 1 0 0 0 0 0 0
F12
F11
F10
F9
F8
F7
REGISTER READ1 X1A Register X2B Register C Register M Register Control Register OFS0 Data Register OFS1 Data Register A/B Select Register 0 A/B Select Register 1 GPIO read (data in F0)2
Bits F12 to F7 select channel to be read back, from Channel 0 = 001000 to Channel 7 = 001111 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 1 1 1 1 1 1 0 1 0 1 1
F6 to F0 are don't care for data readback functions except for GPIO read. F6 to F0 should be 0 for GPIO read
Rev. PrF | Page 21 of 25
AD5362/AD5363
POWER SUPPLY DECOUPLING
In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD5362/AD5363 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. If the AD5362/AD5363 is in a system where multiple devices require an AGND-to-DGND connection, the connection should be made at one point only. The star ground point should be established as close as possible to the device. For supplies with multiple pins (VSS, VDD, VCC), it is recommended to tie these pins together and to decouple each supply once. The AD5362/AD5363 should have ample supply decoupling of 10 F in parallel with 0.1 F on each supply located as close to the package as possible, ideally right up against the device. The 10 F capacitors are the tantalum bead type. The 0.1 F capacitor should have low effective series resistance (ESR) and effective series inductance (ESI), such as the common ceramic types that provide a low impedance path to ground at high frequencies, to handle transient currents due to internal logic switching. Digital lines running under the device should be avoided, because these couple noise onto the device. The analog ground plane should be allowed to run under the AD5362/AD5363 to avoid noise coupling. The power supply lines of the AD5362/AD5363 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching digital signals should be shielded with digital ground to avoid radiating noise to other parts of the board, and should never be run near the reference inputs. It is essential to minimize noise on all VREF lines. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far the best, but not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground plane, while signal traces are placed on the solder side. As is the case for all thin packages, care must be taken to avoid flexing the package and to avoid a point load on the surface of this package during the assembly process.
Preliminary Technical Data
POWER SUPPLY SEQUENCING
When the supplies are connected to the AD5362/AD5363 it is important that the AGND and DGND pins are connected to the relevant ground plane before the positive or negative supplies are applied. In most applications this is not an issue as the ground pins for the power supplies will be connected to the ground pins of the AD5362/AD5363 via ground planes. Where the AD5362/AD5363 is to be used in a hot-swap card care should be taken to ensure that the ground pins are connected to the supply grounds before the positive or negative supplies are connected. This is required to prevent currents flowing in directions other than towards an analog or digital ground.
Rev. PrF | Page 22 of 25
Preliminary Technical Data
INTERFACING EXAMPLES
The SPI interface of the AD5362 and AD5363 are designed to allow the parts to be easily connected to industry standard DSPs and micro-controllers. Figure 11 shows how the AD5362/AD5363 could be connected to the Analog Devices Blackfin(R) DSP. The Blackfin has an integrated SPI port which can be connected directly to the SPI pins of the AD5362 or AD5363 and programmable I/O pins which can be used to set or read the state of the digital input or output pins associated with the interface.
AD536x
SPISELx SCK MOSI MISO SYNC SCLK SDI SDO RESET LDAC CLR BUSY
536x-0101
AD5362/AD5363
the Receive Frame Synchronization (RFS) pin. Similarly the transmit and receive clocks (TCLK and RCLK) are also connected together. The user can write to the AD5362 or AD5363 by writing to the transmit register. A read operation can be accomplished by first writing to the AD5362/AD5363 to tell the part that a read operation is required. A second write operation with a NOP instruction will cause the data to be read from the AD5362/AD5363. The DSPs receive interrupt can be used to indicate when the read operation is complete.
ADSP-21065L
TFSx RFSx TCLKx RCLKx DTxA DRxA FLAG0 FLAG1 FLAG2 FLAG3
AD536x
SYNC SCLK SDI SDO RESET LDAC CLR BUSY
536x-0101
ADSP-BF531
PF10 PF9 PF8 PF7
Figure 12. Interfacing to a ADSP-21065L DSP
Figure 11. Interfacing to an Blackfin DSP
The Analog Devices ADSP-21065L is a floating point DSP with two serial ports (SPORTS). Figure 12 shows how one SPORT can be used to control the AD5362 or AD5363. In this example the Transmit Frame Synchronization (TFS) pin is connected to
Rev. PrF | Page 23 of 25
AD5362/AD5363 OUTLINE DIMENSIONS
8.00 BSC SQ 0.60 MAX 0.60 MAX
43 42
Preliminary Technical Data
0.30 0.23 0.18
56 1
PIN 1 INDICATOR
PIN 1 INDICATOR
TOP VIEW
7.75 BSC SQ
EXPOSED PAD (BOTTOM VIEW)
6.25 6.10 SQ 5.95
0.50 0.40 0.30
29 28
15 14
0.25 MIN 1.00 0.85 0.80 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF 6.50 REF
12 MAX
0.50 BSC SEATING PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VLLD-2
Figure 11. 56 Lead LFCSP Package Dimensions shown in millimeters
0.75 0.60 0.45 SEATING PLANE
1.60 MAX
1
12.00 BSC SQ
52 40 39 PIN 1
TOP VIEW
(PINS DOWN)
10.00 BSC SQ
1.45 1.40 1.35
0.15 0.05
10 6 2
0.20 0.09 7 3.5 0 0.10 MAX COPLANARITY
VIEW A
13 14 26 27
SEATING PLANE
0.65 BSC
0.38 0.32 0.22
VIEW A
ROTATED 90 CCW COMPLIANT TO JEDEC STANDARDS MS-026BCC
Figure 12. 52 Lead LQFP Package Dimensions shown in millimeters
ORDERING GUIDE
Model AD5362BCPZ AD5362BSTZ AD5363BCPZ AD5363BSTZ Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C Package Description 56-Lead LFCSP 52-Lead LQFP 56-Lead LFCSP 52-Lead LQFP Package Option CP-56 ST-52 CP-56 ST-52
Rev. PrF | Page 24 of 25
Preliminary Technical Data NOTES
AD5362/AD5363
(c)2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR05762-0-10/06(PrF)
Rev. PrF | Page 25 of 25

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